A solid state drive (SSD) is designed to provide reliable and high performance storage of user data across a flash-based memory system containing a host interface controller (such as a Serial Advanced Technology Attachment (SATA) interface) and a number of memory multi-chip packages (MCPs), where each MCP contains a stack of NAND flash dies and, optionally, a flash memory controller. The Open NAND Flash Interface (ONFI) protocol provides support for parallel access to multiple NAND dies (or “logical units” (LUNs)) on a single “target” or NAND multi-chip stack on a single shared ONFI channel. In a typical SATA-based SSD application, a central host controller accesses multiple attached devices (targets/NAND device clusters) on each ONFI channel, and across several ONFI channels. (A typical host controller would include a SATA interface and four, eight, or more flash interface channels. These channels may utilize a standard flash interface protocol, such as ONFI.) Each ONFI target typically controls 2, 4, or 8 NAND dies.
Some SSDs have flash storage capable of storing one bit per memory cell (i.e., single level cells (SLCs)) or multiple bits per memory cell (i.e., multi-level cells (MLCs)). Examples of MLCs include X2 technology (two bits per cell) and X3 technology (three bits per cell). There can be programming challenges when writing multiple bits per cells, and it is desired that SSDs ensure reliable storage of user data despite these challenges.